Via Inductance Model
Single via inductance (approximate): L_via ≈ 1 nH/mm of via length Example: Standard 1.6mm FR4 PCB, drill 0.3mm: Signal via through 4-layer board (1.6mm): L ≈ 1.6 nH At 2.4 GHz: X_L = 2π × 2.4GHz × 1.6nH = 24.1 Ω → significant impedance! At 900 MHz: X_L = 9.0 Ω → less significant
Ground Via Requirements
| Frequency | Max Via Spacing | Via Pitch Rule |
|---|---|---|
| 900 MHz | 9 mm | λg/20 on FR4 |
| 2.4 GHz | 3.4 mm | λg/20 on FR4 |
| 5 GHz | 1.8 mm | λg/20 on RO4003C |
| 28 GHz | 0.3 mm | λg/20 on RT5880 |
Reducing Via Inductance
- Parallel vias: two vias in parallel halve inductance (L/2)
- Larger via diameter: slightly reduces L (weak dependence on diameter)
- Shorter vias: use back-drilling or blind vias to minimize length
- Via-in-pad: eliminates via stub length contribution
Via Transition Design for RF Signal Layers
When routing RF signals between layers through a via, compensate for the via's parasitic capacitance and inductance:
Via pad capacitance: C_pad ≈ ε₀εr × A_pad / h (plate capacitor model) Compensation: reduce pad size → reduces C_pad Anti-pad: clearance hole in power planes below signal via → reduces C_pad
RF View: Via inductance affects PCB matching network performance. If measured S11 shows frequency shift from simulation, add a series inductor in the Circuit Simulator to model the via's ~1 nH inductance and verify the match. Free on Android.