RF PCB Stack-Up Fundamentals
The stack-up (layer arrangement, substrate materials, and thickness) directly determines trace impedance, coupling between signals, and insertion loss. A well-designed stack-up is as important as the circuit design itself for RF performance above 1 GHz.
Recommended 4-Layer RF PCB Stack-Up
Layer 1 (top): Signal + RF traces (microstrip, Z₀=50Ω)
Layer 2: Ground plane (solid, no cuts under RF traces)
Layer 3: Power/DC distribution
Layer 4 (bottom): Ground plane (second reference)
Substrate between L1-L2: RF-grade (Rogers RO4003C, 8–20 mil)
Substrate between L2-L4: FR4 (standard, lower cost)
Benefit: RF signals on L1 use Rogers substrate for low loss
Digital and power on L3-L4 use FR4 for cost
50 Ω Trace Width by Layer
| Configuration | H (mm) | Substrate | W for 50 Ω |
|---|---|---|---|
| Microstrip (L1 over L2) | 0.203 | RO4003C | 0.44 mm |
| Microstrip (L1 over L2) | 0.508 | RO4003C | 1.10 mm |
| Microstrip (L1 over L2) | 1.6 | FR4 | 2.95 mm |
| Stripline (between L2 and L4) | total H=1.6 | FR4 | ~0.8 mm (dual ground) |
Ground Via Rules for RF
Via inductance: L_via ≈ 1 nH per mm of via length Rules for RF ground vias: - Spacing: λ_g/20 maximum (at 5 GHz FR4: every 3.2 mm) - Diameter: ≥0.3 mm for good conductance - Multiple vias: parallel vias reduce inductance (2 vias = L/2) - Coplanar transition: via fence around signal path changes
Crosstalk Prevention Between RF Traces
- Minimum spacing between microstrip traces: 3× substrate height H (3H rule)
- Add ground via fence between parallel RF traces above 3 GHz
- Route sensitive receive traces (LNA input) away from transmit traces
- Digital signals on separate layer with dedicated ground plane
RF View Stack-Up Design: Use RF View's Microstrip Calculator to compute 50 Ω trace widths for your specific substrate (εr, H) at each operating frequency. Design layer thickness to achieve target impedance. Free on Android.