What Is S11?
S11 is the (1,1) element of the scattering matrix — the ratio of the reflected wave amplitude at port 1 to the incident wave amplitude at port 1, with all other ports terminated in the reference impedance Z₀ (typically 50 Ω). It directly measures how well the input port is impedance-matched to the system.
Formula
S11 = b₁ / a₁ (with a₂ = 0, port 2 terminated in Z₀) Return Loss (dB) = −20 · log₁₀|S11| [positive number, larger = better] S11 (dB) = 20 · log₁₀|S11| [negative for passive devices] Reflection Coeff Γ = (Z_in − Z₀) / (Z_in + Z₀) S11 = Γ at port 1
S11 / Return Loss / VSWR Conversion Table
| S11 (dB) | Return Loss (dB) | |Γ| | VSWR | Mismatch Loss |
|---|---|---|---|---|
| 0 | 0 | 1.000 | ∞ | ∞ dB |
| −3 | 3 | 0.708 | 5.83 | 3.01 dB |
| −6 | 6 | 0.501 | 3.01 | 1.25 dB |
| −10 | 10 | 0.316 | 1.92 | 0.46 dB |
| −14 | 14 | 0.200 | 1.50 | 0.18 dB |
| −20 | 20 | 0.100 | 1.22 | 0.04 dB |
| −26 | 26 | 0.050 | 1.11 | 0.01 dB |
| −30 | 30 | 0.032 | 1.06 | 0.004 dB |
Typical S11 Specifications by Device Type
| Device | S11 Requirement | Reason |
|---|---|---|
| Antenna (mobile) | < −10 dB across band | VSWR < 1.92, <10% power reflected |
| LTE filter port | < −14 dB (VSWR < 1.5) | Minimal TX/RX path loss |
| LNA input | Often −6 to −10 dB | Optimum noise match ≠ conjugate match |
| PA output | < −10 dB | Stable load, protect PA from reflections |
| PCB connector | < −20 dB to rated freq | Transparent interconnect |
| Cable assembly | < −20 dB | Near-lossless interconnect |
S11 on the Smith Chart
The complex reflection coefficient Γ = |Γ|∠θ maps to a point inside the unit circle. The center of the chart (Γ = 0) represents perfect match (Z = Z₀ = 50 Ω). Moving outward increases |S11|. The upper hemisphere is inductive (positive reactance); the lower is capacitive (negative reactance). Impedance matching on the Smith chart involves moving from the load point toward the chart center using series or shunt reactive elements.
How to Improve S11
- Add a matching network (L/C lumped elements or microstrip stubs) between source and load
- Use the Smith chart to trace the matching path: add series inductance (clockwise arc) or shunt capacitance (counter-clockwise arc on constant-G circle)
- Check layout — PCB via inductance and trace capacitance can detune the match
- Ensure VNA calibration is done at the device reference plane
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