Ground Plane Rules
The ground plane is the most critical element of any RF PCB. Follow these rules:
- Solid copper ground plane on the layer immediately below the RF signal layer — no splits or voids under signal traces
- Stitch vias: Place ground vias every λ/20 along both sides of transmission lines to prevent parasitic slot antenna modes
- Separate digital and RF grounds: Connect at a single star point near the power supply, never under RF circuitry
- Avoid ground plane cuts under matching networks or filters — they change εᵣ_eff and invalidate design calculations
Transmission Line Routing
| Rule | Why |
|---|---|
| Keep lines ≥3× line width from adjacent conductors | Minimize capacitive coupling (crosstalk) |
| Use chamfered or curved corners, not 90° | 90° corners cause ~0.1 dB reflection at >10 GHz |
| Minimize line length | Reduce conductor loss and parasitic resonances |
| Match line width to design calculations | Width tolerance of ±10 μm shifts impedance by ±1–2 Ω |
| Use microstrip for top-layer access | Easier debug and probing |
| Use stripline for >30 dB isolation between adjacent signals | Shielded by ground planes above and below |
Component Placement
- Place RF components first: LNA → filter → PA → antenna in signal chain order
- Keep LNA input short — minimize trace length from antenna/connector to LNA input to reduce noise figure
- Place decoupling capacitors within 0.5 mm of IC power pins
- Orient components to minimize signal path length
- Keep high-power PA away from sensitive LNA — use metal shields if necessary
Decoupling Strategy
RF IC power supply decoupling requires multiple capacitor values in parallel:
| Capacitor | Value | Purpose | Place |
|---|---|---|---|
| Bulk | 10–100 μF | Low-frequency reservoir | Near regulator |
| Ceramic mid | 100 nF | Mid-frequency decoupling | Within 2 mm of IC |
| RF bypass | 10–100 pF | RF frequency decoupling | Within 0.5 mm of IC pin |
Verifying Layout with S-Parameter Measurements
After PCB fabrication, use RF View to load S-parameter measurements and verify layout quality:
- S11 of transmission line stub: should match simulated reflection
- Insertion loss (S21) of critical signal paths: compare to calculated conductor + dielectric loss
- Isolation (S21 between non-connected ports): should meet crosstalk budget
- Batch-load S2P files from multiple board samples to verify process repeatability